Hello, firstly, I would like to say this is a great project both for the utilities it provides and the learning it provides. So, thanks a lot for sharing this awesome work.
I have been working on integrating the instruction cover group of this project into a custom core verification environment that I have been working on in order to make it sample through uvm_monitor alongside the DUT and also support other test suites and custom tests when I faced this issue. To get the riscv_instr_cover_group.sv file up and running, I created a dependency package that would include and import all the necessary data types and functions. However, during the implementation, I realized that even though this project works quite as described when built and run standalone, it had some dependency patterns that puzzled me.
As far as I know, in SystemVerilog, one cannot have circular dependencies (two different classes or packages depending on each other) within a project (i.e., Verification Academy discussion regarding it) However, when I started fiddling with the source files manually, I realized that in line 40 of riscv_instr_gen_config.sv, there is a type data_pattern_t used within the class riscv_instr_gen_config.
and I face a syntax error through VCS regarding the type here, as follows:
Even though the standalone master branch works fine, I thought that this could be a problem and wanted to report it. And possibly, if this is not an issue in this project, how could this work without any issues? Is there a specific methodology employed to overcome this?
Hello, firstly, I would like to say this is a great project both for the utilities it provides and the learning it provides. So, thanks a lot for sharing this awesome work.
I have been working on integrating the instruction cover group of this project into a custom core verification environment that I have been working on in order to make it sample through uvm_monitor alongside the DUT and also support other test suites and custom tests when I faced this issue. To get the riscv_instr_cover_group.sv file up and running, I created a dependency package that would include and import all the necessary data types and functions. However, during the implementation, I realized that even though this project works quite as described when built and run standalone, it had some dependency patterns that puzzled me.
As far as I know, in SystemVerilog, one cannot have circular dependencies (two different classes or packages depending on each other) within a project (i.e., Verification Academy discussion regarding it) However, when I started fiddling with the source files manually, I realized that in line 40 of riscv_instr_gen_config.sv, there is a type data_pattern_t used within the class riscv_instr_gen_config.
https://github.com/chipsalliance/riscv-dv/blob/f0c570d11236f94f9c5449870223a5ac717cc580/src/riscv_instr_gen_config.sv#L39-L40
This type is defined in the riscv_instr_pkg.sv package, lines 1131-1135.
https://github.com/chipsalliance/riscv-dv/blob/f0c570d11236f94f9c5449870223a5ac717cc580/src/riscv_instr_pkg.sv#L1130-L1135
However, riscv_instr_pkg.sv also includes riscv_instr_gen_config.sv in line 1536, which makes these two dependent on each other:
https://github.com/chipsalliance/riscv-dv/blob/f0c570d11236f94f9c5449870223a5ac717cc580/src/riscv_instr_pkg.sv#L1536
and I face a syntax error through VCS regarding the type here, as follows:
Even though the standalone master branch works fine, I thought that this could be a problem and wanted to report it. And possibly, if this is not an issue in this project, how could this work without any issues? Is there a specific methodology employed to overcome this?