chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
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Error: illegal operands `sd s11,sub_4_stack_p(s5)' #969

Closed AhmedAmrAbdellatif1 closed 6 months ago

AhmedAmrAbdellatif1 commented 7 months ago

Hello everyone, I was trying to generate a custom target test to test my RV64I architecture, so when i tried to run this target[1] this error shows up:

$ run --custom_target /target/rv64i --isa rv64i --mabi lp64
...
out_2024-02-07/asm_test/riscv_rand_instr_test_0.S: **Assembler messages:**
out_2024-02-07/asm_test/riscv_rand_instr_test_0.S:**11551: Error: illegal operands `sd s11,sub_4_stack_p(s5)'**

Can anyone help me?

[1]: rv64i target

- import: <riscv_dv_root>/yaml/base_testlist.yaml

- test: riscv_misaligned_instr_test
  description: >
    Test misaligned instruction exception by JALR to an address with addr[0] = 1
  iterations: 2
  gen_test: riscv_instr_base_test
  gen_opts: >
    +instr_cnt=4000
    +num_of_sub_program=8
    +no_csr_instr=1
    +no_fence=1
  rtl_test: core_base_test