chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
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Access Exception error while running spike for rv64imac instructions #971

Open omanzoor opened 9 months ago

omanzoor commented 9 months ago

I generated rv64imac testcases using riscv-dv, when I try to run it using spike iss, spike gives an error:

///////////////////////////////////////////////////////////////////////////// core 0: 3 0x000000008000b120 (0x000e0e13) x28 0x000000008000a11c core 0: 0x000000008000b124 (0x000e00e7) jalr t3 core 0: 3 0x000000008000b124 (0x000e00e7) x1 0x000000008000b128 core 0: >>>> test_done core 0: 0x000000008000a11c (0x00004185) c.li gp, 1 core 0: 3 0x000000008000a11c (0x4185) x3 0x0000000000000001 core 0: 0x000000008000a11e (0x00000073) ecall core 0: exception trap_machine_ecall, epc 0x000000008000a11e Access exception occurred while host was accessing memory on behalf of target (tohost = 0xfffffffffffffff0): Memory address 0xfffffffff8 is invalid ///////////////////////////////////////////////////////////////////////////

What can be the issue and how to fix it?