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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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How to test Atomic Extension? #973

Open AhmedAmrAbdellatif1 opened 5 months ago

AhmedAmrAbdellatif1 commented 5 months ago

I'm working on a GP to design a RV64IMAC, and i want to use the DV to test my design, but there's no test that generates atomic instructions, can someone help me?

MikeOpenHWGroup commented 5 months ago

Hi @AhmedAmrAbdellatif1, simply generating atomic instructions is insufficient. Typically there will be interactions between your core and the memory sub-system that a test-program running on the core cannot check, so your testbench needs to model and check that the right thing(s) happen (example). Before spending a lot of time getting riscv-dv to generate atomic instructions, you can probably do a lot of useful work with manually written test-programs.

Once you are satisfied with that, you could try extending class riscv_directed_instr_stream to generate atomic instructions with riscv-dv. Here is an example of how that can work.

AhmedAmrAbdellatif1 commented 5 months ago

Could i use spike to help me with testing the behavior? if yes, could you guide me how to use it to do so?

MikeOpenHWGroup commented 5 months ago

Could i use spike to help me with testing the behavior?

It depends on the needs of your core. Spike has a limited modelling of the interface(s) to memory and only models what the ISA does.

if yes, could you guide me how to use it to do so?

Sorry, I do not use Spike a lot. I did find the README helpful.