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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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Guide lines to enable virtual address translation? #974

Open mukesh891 opened 5 months ago

mukesh891 commented 5 months ago

Hi, I was currently working to generate page tables for address translations and we are using the following changes to in our base_testlist.yaml: +bare_program_mode=0 +virtual_addr_translation_on=1

With the above changes after init_supervisor_mode method we are actually seeing an error like below while transitioning from machine to supervisor mode:

#0189 0 M 00000000000001aa(init_supervisor_mode+48) 10449073 csrw    sie,s1
#0189 0 M 00000000000001aa RW sie 0000000000000000 -> 0000000000000000
#0190 0 M 00000000000001ae(init_supervisor_mode+4c) 30200073 mret
#0190 0 M 00000000000001ae RW mstatus 0000000a00000800 -> 0000000a00000080
#0190 0 M 00000000000001ae RW 'iss/cpu0', 0x00000000000001b2: Supervisor 0000     illegal
#0190 0 M 00000000000001ae RW MEMRM 0x70026000 0x70026000 8 000000001c009c21 L2 (iss/cpu0/Supervisor DLM data)
#0190 0 M 00000000000001ae RW MEMRM 0x70027000 0x70027000 8 000000001c00a421 L1 (iss/cpu0/Supervisor DLM data)
#0190 0 M 00000000000001ae RW MEMRM 0x70029000 0x70029000 8 00000000200000ef L0 (iss/cpu0/Supervisor DLM data)

Can you please let us know if we are missing something?