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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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Can't do S-mode test ( No delegation ) #975

Open AhmedAmrAbdellatif1 opened 7 months ago

AhmedAmrAbdellatif1 commented 7 months ago

Hello everyone, I've design an RV64IMAC architecture with M & S Privilege levels supported. I want to test the S-mode, I see that the assembly generated has S-mode exception handler and stvec handler, but spike only does M-mode handler exception and mtvec handler.

How can i force spike to go to s-mode exception handler?

Also, how i force spike to use sscratch instead of mscratch?

MikeOpenHWGroup commented 7 months ago

Hi @AhmedAmrAbdellatif1, I am not a member of ChipsAlliance, but I do not believe they maintain/support Spike. I suggest you refer to the Spike documentation. You could also check out this Spike documentaton effort.

AhmedAmrAbdellatif1 commented 7 months ago

Hello @MikeOpenHWGroup, Maybe i wasn't clear enough. but my question is "how to generate test that uses stvec handler and s-mode exception and stuff"

serge0699 commented 2 months ago

Hello @AhmedAmrAbdellatif1, you can use init_privileged_mode option. See riscv_instr_gen_config.sv and riscv_asm_program_gen.sv.