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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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Initial mret (from init_supervisor_mode) sends processor to untranslated address #977

Open talhashahzad12345 opened 6 months ago

talhashahzad12345 commented 6 months ago

I generated tests using target rv64gc

The test has init_supervisor_mode and before that an MEPC setup segment. In mepc setup, only last 12 bits of mepc are kept which is explained in riscv dv's code with a comment stating that only last 12 bits are kept for supervisor or user mode.

mepc_setup():
   800000164:   00000417            auipc   s0,0x0
   800000168:   06240413            addi    s0,s0,98 # 8000001c6 <init>
   80000016c:   1452                    slli    s0,s0,0x34
   80000016e:   9051                    srli    s0,s0,0x34
   800000170:   34141073            csrw    mepc,s0

If we use mret to return, is it not in machine mode and so mepc should be setup per machine mode and complete address should be kept in it?