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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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Request for detailed documentation #978

Open fangzhigang32 opened 3 months ago

fangzhigang32 commented 3 months ago

(1) Is there a more detailed documentation, including the architecture and parameter specifications of the tool. (2) Is there any original paper published on riscv-dv. thank you!

davine47 commented 3 months ago

Hi, here is the riscv-dv guide document, you can also find it in README. As for the implementation of riscv-dv, in vcs flow, it uses a technique similar to the BNF (Backus-Naur Form) to organise the instruction streams or sequences.