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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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Can riscv-dv used with ucb rocket core/boom core? #979

Open Sai-Manish opened 3 months ago

Sai-Manish commented 3 months ago

I would like to understand more on how to integrate other riscv-dv for other cores. Can I find much more detailed documentation on how to use it?

davine47 commented 3 months ago

Hi, riscv-dv is a static random instruction generator, which means that final outputs are bin files. Rocket-chip core provides a instruction bootrom in ExampleRocketSystem.scala, it will read the bin file and then the core can fetch the target instructions.

Sai-Manish commented 3 months ago

Hi @davine47, Thanks for your reply. I have few more questions, 1) Can we use verilator for the yaml flow? If yes, is there any compiler.yaml file which has verilator setup in it? 2) Instead of adding the bin file into bootrom is there any other way I can verify the core? like similar to torture tests. 3) I am not able generate the binary file following the steps in README.md