Open Sai-Manish opened 3 months ago
Hi, riscv-dv is a static random instruction generator, which means that final outputs are bin files. Rocket-chip core provides a instruction bootrom in ExampleRocketSystem.scala, it will read the bin file and then the core can fetch the target instructions.
Hi @davine47, Thanks for your reply. I have few more questions, 1) Can we use verilator for the yaml flow? If yes, is there any compiler.yaml file which has verilator setup in it? 2) Instead of adding the bin file into bootrom is there any other way I can verify the core? like similar to torture tests. 3) I am not able generate the binary file following the steps in README.md
I would like to understand more on how to integrate other riscv-dv for other cores. Can I find much more detailed documentation on how to use it?