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chipsalliance / riscv-dv

Random instruction generator for RISC-V processor verification
Apache License 2.0
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run: fix disabling the `c` extension #988

Open fkokosinski opened 1 month ago

fkokosinski commented 1 month ago

This PR fixes the way that the c extension is disabled, i.e. removed from the arch ISA string. Without this change, for GCC versions where Zicsr and Zifencei constitute separate extensions, the following ISA string:

  rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs

Would be changed to (note incorrect _zisr vs correct _zicsr):

  rv32im_zisr_zifenei_zba_zbb_zb_zbs

Instead of the expected:

  rv32im_zicsr_zifencei_zba_zbb_zbc_zbs