chipsalliance / riscv-vector-tests

Unit tests generator for RVV 1.0
Apache License 2.0
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Need more test case for vector index load/store #12

Closed huxuan0307 closed 6 months ago

huxuan0307 commented 1 year ago

The vector extension allows index load insts to use different width of data and index. For example:

vsetvli t1, t0, e8,m1,ta,ma
vluxei64.v v1, (a0), v2

vsetvli t1, t0, e16,m1,ta,ma
vluxseg2ei64.v v2, (a0), v4
ksco commented 1 year ago

Thanks for the feedback, will take a look tomorrow.

ksco commented 1 year ago

Added support for different data/offset widths in the above commit, sorry for the delay. The generated tests look good for me now, feel free to reopen this if there is any follow-up issue.

jerryz123 commented 1 year ago

@ksco That patch results in code that causes accesses to undefined/out-of-bounds regions. I do make VLEN=256 SPLIT=2000 MODE=virtual, which results in two types of failures:

IMO, the easiest way to resolve this is to fold in the index-generation and indexed-data generation into a single step, so the generator can guarantee that all indexed accesses like within the generated region.

Segmented loads/stores make this more complex as well.

jerryz123 commented 1 year ago

Oops I forgot, my make command only works with latest riscv-test-env, that should be bumped

ksco commented 1 year ago

Ok, let me bump it and try.

ksco commented 1 year ago

Fixed, the main issue is we are using the same data section for all split tests, while it's okay for non-virtual env, I think it's sometimes too large for the virtual env. Anyway, I split the data section in above commit, and it works.

ksco commented 1 year ago

Currently it's only a workaround, the generator code is ugly and certainly needs some refactoring.