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chipsalliance / riscv-vector-tests

Unit tests generator for RVV 1.0
Apache License 2.0
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Tests for vsext.vf4/8 and vzext.vf4/8 rely on inital values of vector registers #26

Closed troibe closed 9 months ago

troibe commented 9 months ago

The simulator I'm working on currently marks unitialized (vector) registers with baadf00d. With this the test cases for vsext.vf4/8 and vzext.vf4/8 don't pass as they rely on unitialized vector registers:

    800188f4:   00200293            li  t0,2
    800188f8:   0d92f357            vsetvli t1,t0,e64,m2,ta,ma
    800188fc:   4902a457            vsext.vf4   v8,v16,v0.t
    80018900:   00001517            auipc   a0,0x1
    80018904:   70050513            add a0,a0,1792 # 8001a000 <begin_signature>
    80018908:   fff00293            li  t0,-1
    8001890c:   0db2f357            vsetvli t1,t0,e64,m8,ta,ma
    80018910:   02057427            vse64.v v8,(a0)

In the generated example assembly above vsext.vf4 is executed with lmul=2 (max updated registers v8, v9). When checking the results with vse64.v we then use lmul=8 which accesses vectors v8-v15. However only v8-v11 have been set by prior writes, v12-v15 are still set to baadf00d. (Spike seems to have zero initialized v12-v15) If I force all vector registers to be zero initialized for the tests, then the tests pass.

Should the tests have a section that initializes all vector registers to zero? Or would it be better to not have tests that access vector registers that have not been written to yet? Or is zero initialization required by the spec anyways and I just missed it?

troibe commented 9 months ago

Wrong statement on my side we have these lines above the example assembly that initialize the vector registers as they should:

    800188b8:   84c50513            add a0,a0,-1972 # 8001a100 <testdata>
    800188bc:   000037b7            lui a5,0x3
    800188c0:   a407879b            addw    a5,a5,-1472 # 2a40 <_start-0x7fffd5c0>
    800188c4:   00f50533            add a0,a0,a5
    800188c8:   fff00293            li  t0,-1
    800188cc:   0db2f357            vsetvli t1,t0,e64,m8,ta,ma
    800188d0:   02057407            vle64.v v8,(a0)

I guess then the memory region that it is loading from is unitialized which is also odd.