search

chipsalliance / riscv-vector-tests

Unit tests generator for RVV 1.0
Apache License 2.0
58 stars 19 forks source link

[GSOC] integrated support for Zvbc #42

Closed SyedHassanUlHaq closed 2 months ago

ksco commented 2 months ago

Sorry, why this is closed?

SyedHassanUlHaq commented 2 months ago

Sorry, why this is closed?

My GSOC mentor Zewen told me that we are not going to support some instructions with SEW=64. So we can skip these SEW=64 instructions and I can close the PR

ksco commented 2 months ago

Okay, but the PR is good, so why not merge it? I just need an explanation about valid SEW values.

SyedHassanUlHaq commented 2 months ago

image

here it states that LMUL >= SEWmin/ELEN. So for a instruction that only supports SEW=64, SEWmin=64 and ELEN=64 Hence LMUL >= 1

ksco commented 2 months ago

I see, can you make another PR so we can merge this in?

SyedHassanUlHaq commented 2 months ago

sure