How to work with the Rocket Chip

[FringsA]

Hi, i am new to the Rocket Core and have some problems using it.

There are many sources explaining how to change the configuration of the Rocket Core, but i am struggling to find a documentation on how to use the generated core in my system e.g. executing a program that involves the Rocket Core.

I am looking for something like this, which describes how to get the Rocket Core into the Vivado environment and how to work with it, but there the used source code magically appears from a linked zip file. These files implement the G extension for the RISC-V ISA, for which i do not have the capacity. My question is: How can i generate these 4 files myself with my own configuration? RV64G.Core.v RISCV_Rocket_Core_RV64G_AXI.v
RV64G.HostIO.Adapter.v RISCV_Rocket_Core_RV64G.v

When i follow the instruction of the previous tutorial i get a very different outcome. First of all: The mentioned fsim directory (second last line of code) does not exist in my repository. Therefore i am changing into the vsim directory, which contains vlsi_mem_gen file, which generates the verilog code. My new directory generated-src contains these files:

consts.DefaultConfig.vh DefaultConfig.graphml rocketchip.DefaultConfig.conf rocketchip.DefaultConfig.prm DefaultConfig.cfg DefaultConfig.knb rocketchip.DefaultConfig.d rocketchip.DefaultConfig.v DefaultConfig.cst rocketchip.DefaultConfig.behav_srams.v rocketchip.DefaultConfig.fir

What do i have to do with these? rocketchip.DefaultConfig.v looks like it is the verilog code for the Rocket Core. Is this assumption correct?

My final goal is to run Linux on the PS and have it communicating with the Rocket Core (running on the PL). The Rocket Core is supposed to work as a co-processor and communicate with the PS and its components (e.g. memory) via AXI. My guess is that this communication will be using the on-chip memory. The problem here is: Linux does not allow direct access to the memory, where as the Rocket Core has a defined memory management table for the DMA. I have already succeeded to boot Linux on the PS.

How can i connect this core to my PS (processing system) and let them communicate with each other?

Is it possible to just reuse the standard Rocket Core to communicate via AXI or do i have to modify the Rocket Core sources?

I had a look on the fpga-zynq repository and could execute root@zynq:~# ./fesvr-zynq pk hello, but i am missing the documentation on how to connect it to the PS and how to use the Rocket Core e.g. reading something from the DDR and work with it. All i found was a "If you wish to make any modifications to the project, you may now do so." in chapter 3.2

For all i can see i have to connect the HP0 port from the PS with a htif/HostIO port from the Rocket Core, but i have not found any documentation. Here that states this interface is discontinued.

I also had a look into the RISC-V documentation, but it does not cover how to use it.

Settings:

OS: Ubuntu 16.04 LTS Vivado version: 2017.4 Board: Zynq Zybo XC7Z010-1CLG400C Repository: fpga-zynq commit 86d2cf1

Thanks

[CLappin]

Hi @FringsA ,

Yes the two verilog files (.v) will need to be added to the Vivado packager, along with the some of the files from the vsrc folder (AsyncResetReg.v and plusarg_reader.v). The default config (if you've built the tools for 64 bit (i think )) should be an RISC-V 64 bit IMAFDC.

I'm not to sure about the Zynq/ Linux specific questions though. There is a major learning curve with chisel and rocket-chip but once you get through the first few weeks/months it starts to get easier.

Regards, Ciaran

[eliaskousk]

I'll make some points based on your message:

1. It's best if you use the official fpga-zynq repo from the UCB-Bar guys since a lot has changed since I used RISC-V for the GSoC project. Unless you have a parallella board to test the RISC-V core there is no reason to use my Github project or blog instructions. Of-course you can read the blog posts to learn more about these things but I wouldn't recommend following the exact instructions or code since nothing will work out of the box 2 years later, without small but needed modifications.

2. Before replying to you I tried updating everything on my Github repo to the latest RISC-V developments + Vivado 2017.4 but it seems this is a bigger task than expected. I eventually abandoned it after 3-4 hours of work due to various errors I encountered that although I can fix them I will definitely need more time.

3. Your biggest concern as I see it is this: "Do you know how i can connect this core to my PS (processing system) and let them communicate with each other?" If you follow the fpga-zynq repo's guidelines (or mine) and run the scripts for your board you will eventually have communication between the PS (ARM) + PL (RISC-V).

For example you mentioned that you run the hello binary through the pk proxy kernel. This actually does what you need. The hello binary runs on the RISC-V (PL) but has the ability to r/w DDR memory through the ARM (PS). Of-course this is a hello program that doesn't do writes or reads to the memory but you certainly can change the program or build a new one to do so. Maybe I don't understand what you are trying to do, if so please explain more.

4. The HostIO interface is indeed discontinued but it as far as I know it has been replaced with a new serial interface that does the same thing. Both the old and the new interfaces need the fesvr (front end server) running on Zynq's PS in order to boot the RISC-V processor on the PL and load it an application binary (through pk - proxy kernel) or kernel (through bbl - berkeley boot loader).

5. The interface for Zynq PS - PL communication (named ZynqAdapter) that in turn uses the above new serial interface (or the old Host I/O) is instantiated and connected to the RISC-V core with the following 'WithZynqAdapter' configuration of rocket-chip found in the fpga-zynq repo:

https://github.com/ucb-bar/fpga-zynq/blob/master/common/src/main/scala/Configs.scala

If you use the repo's instructions and scripts you don't have to specify it or do something with it yourself (being in Chisel is also difficult if you don't know Chisel). The scripts in the fpga-zynq do exactly that.

If on the other hand you are generating a rocket core manually in your own flow you have to provide it so that it builds the ZynqAdapter and connect it to the core giving it access to the two AXI interfaces (one master to r/w the DDR and one slave to accept the boot configuration and the boot binary -> pk or bbl).

In that manual case You just have to make sure that whenever you are generating the rocket core you do it with CONFIG=ZynqFPGAConfig (or ZynqMediumFPGAConfig, ZynqSmallFPGAConfig). These are found at the end of the above scala configuration file.

6. Yes the RISC-V core and the needed interface is contained on the file named rocketchip.ConfigName.v where ConfigName = DefaultFPGAConfig (if you follow the main rocket chip repo) or ZynqFPGAConfig (if you follow the fpga-zynq repo). You can safely ignore all the other generated files in your attempt to better package the generated HDL if for example you wish to package it in your tool of choice (e.g Vivado's IP packager).

Edit: Based on @CLappin 's reply it seems that with the latest version of rocket chip you might have to add a couple more files as he says if you wish to package a generated rocket core.

[CLappin]

Just to follow up I was playing with one of the later repositories and it seems that all the necessary files are added by the make file to the generated_src folder. Apologies for any misleading information on my part.

[jjtoms4s]

hellow i need to use rocket core in my own soc system ,what i get is same as Eliaskousk consts.DefaultConfig.vh DefaultConfig.graphml rocketchip.DefaultConfig.conf rocketchip.DefaultConfig.prm DefaultConfig.cfg DefaultConfig.knb rocketchip.DefaultConfig.d rocketchip.DefaultConfig.v DefaultConfig.cst rocketchip.DefaultConfig.behav_srams.v rocketchip.DefaultConfig.fir does the "rocketchip.DefaultConfig.v" file contains the details of whole rocktet-core,do i only need to add this file into my soc system or do i need others. by the way i used to use arm's sc000-core,which contains a lot of verilog files ,i think there should be more than one file for rocket core,am i right?

[CLappin]

The two verilog files that are generated contains most of the verilog. There are some extra verilog files that Rocket chip uses, that (from my previous post) should be in the generated-src folder. If not take a look in src/main/scala or src/main. The extra files. In total you should only need about 4 files, the default config, Sram, plusarg and asyncreset.

Sorry posting from my phone so can't give you proper links.

Cheers, Ciaran

[eliaskousk]

@jjtoms4s I'm replying to your answer on an email I got but I can't see here.

The top component is called 'top' and has I/O ports for clock, reset and AXI links. You can find an instantiation in the following wrapper along with a Xilinx Zynq block design: https://github.com/ucb-bar/fpga-zynq/blob/master/common/rocketchip_wrapper.v

[apullin]

The fpga-zynq README now states that it is out of sync with the rocketchip master.

Should it still be expected to work to generate a working wrapper, adapter, etc around a core generated from rocketchip?

[Mixermachine]

The fpga-zynq README now states that it is out of sync with the rocketchip master.

Should it still be expected to work to generate a working wrapper, adapter, etc around a core generated from rocketchip?

There is a fork of the original repo -> https://github.com/donggyukim/fpga-zynq Sadly it does not contain the Zybo folder that is needed for the original zybo board. I'm currently trying to fix this (can not guarantee that).

[whutmsy]

@eliaskousk I want have communication between the PS (X86) + PL (RISC-V). Does Riscv-fesvr work？

[botaichang]

Hi @eliaskousk, in fescv-zynq (ARM + RISCV(rocket chip)) system, I can launch riscv linux by

LD_LIBARARY_PATH=./ ./fescv-zynq ./bbl 

after launch riscv linux, If I generate some files in riscv linux, how can I export these files out to arm linux filesystem.

And if i want to enlarge the memory size of riscv linux filesystem ,how should i do?

[michael-etzkorn]

Another example of discussion that happens because we need #2960

Closing as user issue that has been stale (though could also move to discussion)