Some doubts about interrupt and assembler.

[clx782782]

I want to implement timer interrupt.

After I use asm volatile("li t0,0x08\n" "csrrs zero,mstatus,t0\n"),I successfully create the executable file.

But when I run it with spike pk ,the terminal tells me:

z  0000000000000000 ra 00000000000100e2 sp 000000007f7e9b40 gp 00000000000123d8
tp 0000000000000000 t0 0000000000000008 t1 0000000000000000 t2 0000000000000000
s0 000000007f7e9b50 s1 0000000000000000 a0 0000000000000001 a1 000000007f7e9b58
a2 0000000000000000 a3 0000000000000001 a4 0000000000000010 a5 0000000000000002
a6 000000000000001f a7 0000000000000000 s2 0000000000000000 s3 0000000000000000
s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
pc 00000000000101a4 va 000000003002a073 insn       3002a073 sr 8000000200046020
An illegal instruction was executed!

I don't know what's wrong.Maybe I haven't get the Machine-mode priority?But how could I get the Machine-mode priority?By Trap?By exception?

I've saw the “risc-v-spec-v2.2" and "riscv-privileged-v1.10" but I'm still in chaos.

Any suggesstion would be greatly appreciated.

[aswaterman]

The problem is that mstatus is an M-mode CSR, but programs running on pk run in U-mode, so they do not have access to M-mode CSRs.

[clx782782]

OK,I see.

Is there no way to possess M-mode by pk ?

If I want to possess M-mode,what need I do?

[aswaterman]

The easiest thing to do is to not use pk. You can write bare-metal programs that are linked to start at address 0x80000000 and they will execute in M-mode. The programs in riscv-tests are all examples of this.

[clx782782]

You mean ./fesvr pk on zedboard also couldn't get M-mode?

How should I run the bare-metal program on zedboard(I only have this board)?

[aswaterman]

You can just run the program with fesvr in place of pk. Try building one of the riscv-tests, like rv64ui-p-add, then run it with ./fesvr rv64ui-p-add

[clx782782]

Very nice guidance!

Let me have a try. (＾▽＾)

[clx782782]

Here is my own asm program(reference resources：https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md#constants):

#include "riscv_test.h"
#include "test_macros.h"

RVTEST_RV64U
RVTEST_CODE_BEGIN
.equ UART_BASE, 0x40003000
.equ REG_RBR, 0
.equ REG_TBR, 0
.equ REG_IIR, 2
.equ IIR_TX_RDY, 2
.equ IIR_RX_RDY, 4

.section .text
.globl _start

1:      auipc a0, %pcrel_hi(msg)    # load msg(hi)
        addi a0, a0, %pcrel_lo(1b)  # load msg(lo)
2:      jal ra, puts
3:      j 3b

puts:
        li a2, UART_BASE
1:      lbu a1, (a0)
        beqz a1, 3f
2:      lbu a3, REG_IIR(a2)
        andi a3, a3, IIR_TX_RDY
        beqz a3, 2b
        sb a1, REG_TBR(a2)
        addi a0, a0, 1
        j 1b
3:      ret
RVTEST_CODE_END 

RVTEST_DATA_BEGIN
.section .rodata
msg:
    .string "Hello World\n"
RVTEST_DATA_END

The building process is successful:

root@c:/home/chang/fpga-zynq/rocket-chip/riscv-tools/riscv-tests/isa# riscv64-unknown-elf-gcc -march=rv64g -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/home/chang/fpga-zynq/rocket-chip/riscv-tools/riscv-tests/isa/../env/p -I/home/chang/fpga-zynq/rocket-chip/riscv-tools/riscv-tests/isa/macros/scalar -T/home/chang/fpga-zynq/rocket-chip/riscv-tools/riscv-tests/isa/../env/p/link.ld rv64ui/const.S -o rv64ui-p-const
root@c:/home/chang/fpga-zynq/rocket-chip/riscv-tools/riscv-tests/isa#

But the emulation in emulator gets error:

root@c:/home/chang/fpga-zynq/rocket-chip/emulator# ./emulator-freechips.rocketchip.system-DefaultConfig +verbose $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-const 2>&1 | spike-dasm
...
0000] R[r18=0000000000000003] inst=[7b200073] dret (args unknown)
C0:     124015 [0] pc=[000000085c] W[r 0=100a2636f7cf5079][0] R[r 0=0000000000000000] R[r18=0000000000000003] inst=[7b200073] dret (args unknown)
C0:     124016 [0] pc=[000000085c] W[r 0=100a2636f7cf5079][0] R[r 0=0000000000000000] R[r18=0000000000000003] inst=[7b200073] dret (args unknown)
*** FAILED *** (tohost = 668)
C0:     124017 [0] pc=[000000085c] W[r 0=100a2636f7cf5079][0] R[r 0=0000000000000000] R[r18=0000000000000003] inst=[7b200073] dret (args unknown)
*** FAILED *** via dtm (code = 668, seed 1525261526) after 124028 cycles
root@c:/home/chang/fpga-zynq/rocket-chip/emulator# 

Any suggestions will be appreciated.

[clx782782]

The another more simple test:

#include "riscv_test.h"
#include "test_macros.h"

RVTEST_RV64U
RVTEST_CODE_BEGIN

.equ CONSTANT, 0xcafebabe

        li a0, CONSTANT

RVTEST_CODE_END 

RVTEST_DATA_BEGIN

RVTEST_DATA_END

It also gets this kind of error: FAILED (tohost = 668)

C0:      33337 [1] pc=[0080000040] W[r30=0000000080001040][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00001f17] auipc   t5, 0x1
*** FAILED *** via dtm (code = 668, seed 1525289145) after 33348 cycles
root@c:/home/chang/fpga-zynq/rocket-chip/emulator# 

[clx782782]

Resolved,that because the format of my program is not completely right.

Thanks again!

[clx782782]

Sir,can I ask you why linking to start at address 0x80000000 will make the program execute in M-mode?Now I could run my program in M-mode but I wonder why.

The easiest thing to do is to not use pk. You can write bare-metal programs that are linked to start at address 0x80000000 and they will execute in M-mode. The programs in riscv-tests are all examples of this.