Read Clear register

[aicr]

Hi ,

I'm trying to implement a status register ,meaning it is updated by HW and cleared upon reading it (back to 0), My problem is, that I don't see the clear operation happening. It isnt being updated by the HW between writes as the conditions for that are not met. here Is the code I wrote (a real test case):

val FifoUnderFlow = Reg(init = Bool(false)) 

val fifo =Module(new AsyncQueue(UInt(width = c.bitwidth),c.depth,3,true,true)) 

// read attempt while not valid
when(!fifo.io.deq.valid & fifo.io.deq.ready) {
    FifoUnderFlow     := Bool(true)
 }

regmap(
       0x0 -> Seq(RegField(1, FifoUnderFlow, RegFieldDesc(" fifo underflow","This Bit indicates that there 
                   was at least one read attempt while empty", access = RegFieldAccessType.R, 
                   rdAction =  Some(RegFieldRdAction.CLEAR)))
       )
  ) 

What am I missing ? how can I clear the register upon read (I still want the the value before the clear). My guess is , that I probably need to add some functionality to the above "FifoUnderFlow", but I haven't found an example for that.

Any pointers will be appreciated, thanks.

[aicr]

If I got it correctly, I have to implement the "RegReadFn" to implement the read clear functionality. Does someone can elaborate on how to hook the register FifoUnderFlow from my code to the "RegReadFn" ?

Also, correct me if I'm wrong, but didn't find any use of rdAction in the rocket-chip code. Am I missing something?

Thanks.

[aicr]

Tried to implement RegReadFn as follow: 0x0 -> Seq(RegField.r(1,RegReadFn{(ready => FifoUnderFlow := ,Bool(false);(Bool(true), FifoUnderFlow)} ,RegFieldDesc("TX fifo underflow","This Bit indicates that there was at least one read attempt while emty")))

In this case the "FifoUnderFlow " register got eliminated (probably connected to constant). Any Ideas ?