Loading Rocket Core on Zedboard by Vivado

[angi10]

Hello everyone, my goal is to build Rocket Core on the Zedboard. I have generate the Rocket Core with DefaultSmallConfig, and i have the output files:

freechips.rocketchip.system.DefaultSmallConfig.0x0.0.regmap.json freechips.rocketchip.system.DefaultSmallConfig.0x0.1.regmap.json freechips.rocketchip.system.DefaultSmallConfig.0x2000000.0.regmap.json freechips.rocketchip.system.DefaultSmallConfig.0x40.0.regmap.json freechips.rocketchip.system.DefaultSmallConfig.0xc000000.0.regmap.json freechips.rocketchip.system.DefaultSmallConfig.anno.json freechips.rocketchip.system.DefaultSmallConfig.behav_srams.v freechips.rocketchip.system.DefaultSmallConfig.conf freechips.rocketchip.system.DefaultSmallConfig.d freechips.rocketchip.system.DefaultSmallConfig.dts freechips.rocketchip.system.DefaultSmallConfig.fir freechips.rocketchip.system.DefaultSmallConfig.graphml freechips.rocketchip.system.DefaultSmallConfig.json freechips.rocketchip.system.DefaultSmallConfig.memmap.json freechips.rocketchip.system.DefaultSmallConfig.plusArgs freechips.rocketchip.system.DefaultSmallConfig.rom.conf freechips.rocketchip.system.DefaultSmallConfig.v

I tried creating a new project in Vivado, adding as sources the two verilog files ...DefaultSmallConfig.v and ...DefaultSmallConfig.behav_srams.v plus the other files required like pulsarg_reader.v, AsyncResetReg.v and EICG_wrapper.v

First of all, i have a syntax error in DefaultSmallConfig.behav_srams.v in line 221, the message is: integer overflow when computing array size

[hyf6661669]

Hi, what is the content of DefaultSmallConfig.behav_srams.v?

[aswaterman]

The error you're seeing comes from the simulated main memory in the test harness; it is not meant to be synthesized. Can you try setting the top-level module in your synthesis experiment to ExampleRocketSystem and see if the problem goes away?

In the longer term, we should consider splitting the Verilog for the DUT from that of the test harness so that the synthesis tool never sees these other modules.

[angi10]

You're right, i've set the module ExampleRocketSystem as top module and the elaboration has been done.

I've another question, is DefaultSmallConfig.v file the verilog description only of the rocket core or of the entire system? I post below some images to help you understanding what i'm looking to know.

Is that file a description of the Rocket core displayed in tile2, or is a description of the system including the networking to external memories? Thanks

[aswaterman]

Cool.

It’s a description of a “core complex”, i.e., the Rocket core, caches/TIMs, MMIO network, interrupt controller, and AXI bridge.

On Tue, Dec 3, 2019 at 6:46 AM angi10 notifications@github.com wrote:

You're right, i've set the module ExampleRocketSystem as top module and the elaboration has been done.

I've another question, is DefaultSmallConfig.v file the verilog description only of the rocket core or of the entire system? I post below some images to help you understanding what i'm looking to know.

[image: Schermata da 2019-12-03 16-41-22] https://user-images.githubusercontent.com/56120355/70061027-ddbafc80-15e3-11ea-81d5-2ad22c94e057.png Is that file a description of the Rocket core displayed in tile2, or is a description of the system including the networking to external memories? Thanks

— You are receiving this because you commented.

Reply to this email directly, view it on GitHub https://github.com/chipsalliance/rocket-chip/issues/2211?email_source=notifications&email_token=AAH3XQWRIMRLXAH2GOSMZFLQWZWMZA5CNFSM4JS7FOCKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEFZTVHY#issuecomment-561199775, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAH3XQQBNGEDSLXIHKTLBBLQWZWMZANCNFSM4JS7FOCA .

[angi10]

Thanks a lot!

[DecodeTheEncoded]

The error you're seeing comes from the simulated main memory in the test harness; it is not meant to be synthesized. Can you try setting the top-level module in your synthesis experiment to ExampleRocketSystem and see if the problem goes away?

In the longer term, we should consider splitting the Verilog for the DUT from that of the test harness so that the synthesis tool never sees these other modules.

In the longer term, we should consider splitting the Verilog for the DUT from that of the test harness so that the synthesis tool never sees these other modules. Have you already done this?( splitting the Verilog for the DUT from that of the test harness??)