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Rocket Chip Generator
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Memory model access delays in emulator #2223

Closed miniskar closed 4 years ago

miniskar commented 4 years ago

Does the Rocket-chip emulator (using verilator) models main memory access delays ?

aswaterman commented 4 years ago

IIRC we are using a fixed-latency memory in the testbench, so cache refills will be artificially fast in simulation.

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Does the Rocket-chip emulator (using verilator) models main memory access delays ?

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miniskar commented 4 years ago

Is this a configurable parameter in some file?

aswaterman commented 4 years ago

It's static in the scala code.

https://github.com/chipsalliance/rocket-chip/blob/54237b5602a273378e3b35307bb47eb1e58cb9fb/src/main/scala/system/SimAXIMem.scala#L32

https://github.com/chipsalliance/rocket-chip/blob/42ae146a02617d8d8be9d965554f0c566b7445ae/src/main/scala/system/SimAXIMem.scala