michael-etzkorn
commented
2 years ago Did you add CanHaveMasterAHBMMIOPort to your system's traits? Is ExtBusAHB replacing ExtBus or are you writing ExtBus => ExtBusAHB in your WithDefaultMMIOPort config?
In Chipyard/generators/Rocket-chip/src/main/scala/SubSystem/Config.scala In Class WithDefaultMMIOPort, I change the ExtBus => ExtBusAHB
In Chipyard/generators/Rocket-chip/src/main/scala/SubSystem/Port.scala I create trait CanHaveMasterAHBMMIOPort,
But the generated file still doesn't exist AHB MMIO port. Is any where wrong in my code? Or How can I do to generate the AHB MMIO Port.
/* Adds a AHB port to the system intended to master an MMIO device bus / trait CanHaveMasterAHBMMIOPort { this: BaseSubsystem => private val mmioPortParamsOpt = p(ExtBusAHB) private val portName = "mmio_port_ahb" private val device = new SimpleBus(portName.kebab, Nil)
val mmioAHBNode = AHBMasterSinkNode( mmioPortParamsOpt.map(params => AHBSlavePortParameters( slaves = Seq(AHBSlaveParameters( address = AddressSet.misaligned(params.base, params.size), resources = device.ranges, regionType = RegionType.UNCACHED, executable = params.executable, supportsWrite = TransferSizes(1, params.maxXferBytes), supportsRead = TransferSizes(1, params.maxXferBytes))), beatBytes = params.beatBytes, lite = true )).toSeq)
mmioPortParamsOpt.map { params => sbus.coupleTo(s"portnamed$portName") { (mmioAHBNode // := AHBLite() := TLToAHB() := _) } } val mmio_ahb = InModuleBody { mmioAHBNode.makeIOs() } }