I tried to use another config other than DefaultConfig when making, but was warned the following:
cd vsim
make CONFIG=DefaultRV32Config
mkdir -p /home/hujiyong/RISCV/rocket-chip/vsim/generated-src/
cd /home/hujiyong/RISCV/rocket-chip && java -Xmx2G -Xss8M -cp /home/hujiyong/RISCV/rocket-chip/rocketchip.jar freechips.rocketchip.system.Generator -td /home/hujiyong/RISCV/rocket-chip/vsim/generated-src -T freechips.rocketchip.system.TestHarness -C DefaultRV32Config
Exception in thread "main" java.lang.Exception: Unable to find part "DefaultRV32Config" from "List(DefaultRV32Config)", did you misspell it or specify the wrong package path?
at Chisel.package$throwException$.apply(compatibility.scala:555)
at freechips.rocketchip.util.HasRocketChipStageUtils.$anonfun$getConfig$1(GeneratorUtils.scala:19)
at scala.collection.immutable.List.foldRight(List.scala:352)
at freechips.rocketchip.util.HasRocketChipStageUtils.getConfig(GeneratorUtils.scala:14)
at freechips.rocketchip.util.HasRocketChipStageUtils.getConfig$(GeneratorUtils.scala:13)
at freechips.rocketchip.stage.phases.PreElaboration.getConfig(PreElaboration.scala:18)
at freechips.rocketchip.stage.phases.PreElaboration.transform(PreElaboration.scala:29)
at freechips.rocketchip.stage.phases.PreElaboration.transform(PreElaboration.scala:18)
at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
at firrtl.Utils$.time(Utils.scala:181)
at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
at freechips.rocketchip.system.RocketChipStage.run(RocketChipStageGenerator.scala:44)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at logger.Logger$.makeScope(Logger.scala:135)
at firrtl.options.Stage.transform(Stage.scala:47)
at firrtl.options.Stage.execute(Stage.scala:58)
at firrtl.options.StageMain.main(Stage.scala:71)
at freechips.rocketchip.system.Generator.main(RocketChipStageGenerator.scala)
Caused by: java.lang.ClassNotFoundException: DefaultRV32Config
at java.base/jdk.internal.loader.BuiltinClassLoader.loadClass(BuiltinClassLoader.java:581)
at java.base/jdk.internal.loader.ClassLoaders$AppClassLoader.loadClass(ClassLoaders.java:178)
at java.base/java.lang.ClassLoader.loadClass(ClassLoader.java:522)
at java.base/java.lang.Class.forName0(Native Method)
at java.base/java.lang.Class.forName(Class.java:315)
at freechips.rocketchip.util.HasRocketChipStageUtils.$anonfun$getConfig$1(GeneratorUtils.scala:16)
... 35 more
make: *** [/home/hujiyong/RISCV/rocket-chip/vsim/Makefrag-verilog:13: /home/hujiyong/RISCV/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultRV32Config.fir] Error 1
hujiyong@7562b1c9fc9c:~/RISCV/rocket-chip/vsim$ make verilog CONFIG=DefaultRV32Config
mkdir -p /home/hujiyong/RISCV/rocket-chip/vsim/generated-src/
cd /home/hujiyong/RISCV/rocket-chip && java -Xmx2G -Xss8M -cp /home/hujiyong/RISCV/rocket-chip/rocketchip.jar freechips.rocketchip.system.Generator -td /home/hujiyong/RISCV/rocket-chip/vsim/generated-src -T freechips.rocketchip.system.TestHarness -C DefaultRV32Config
Exception in thread "main" java.lang.Exception: Unable to find part "DefaultRV32Config" from "List(DefaultRV32Config)", did you misspell it or specify the wrong package path?
at Chisel.package$throwException$.apply(compatibility.scala:555)
at freechips.rocketchip.util.HasRocketChipStageUtils.$anonfun$getConfig$1(GeneratorUtils.scala:19)
at scala.collection.immutable.List.foldRight(List.scala:352)
at freechips.rocketchip.util.HasRocketChipStageUtils.getConfig(GeneratorUtils.scala:14)
at freechips.rocketchip.util.HasRocketChipStageUtils.getConfig$(GeneratorUtils.scala:13)
at freechips.rocketchip.stage.phases.PreElaboration.getConfig(PreElaboration.scala:18)
at freechips.rocketchip.stage.phases.PreElaboration.transform(PreElaboration.scala:29)
at freechips.rocketchip.stage.phases.PreElaboration.transform(PreElaboration.scala:18)
at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280)
at firrtl.Utils$.time(Utils.scala:181)
at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
at firrtl.options.PhaseManager.transform(DependencyManager.scala:443)
at freechips.rocketchip.system.RocketChipStage.run(RocketChipStageGenerator.scala:44)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
at firrtl.options.Translator.transform(Phase.scala:248)
at firrtl.options.Translator.transform$(Phase.scala:248)
at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:183)
at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:179)
at scala.collection.immutable.List.foldLeft(List.scala:79)
at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at logger.Logger$.makeScope(Logger.scala:135)
at firrtl.options.Stage.transform(Stage.scala:47)
at firrtl.options.Stage.execute(Stage.scala:58)
at firrtl.options.StageMain.main(Stage.scala:71)
at freechips.rocketchip.system.Generator.main(RocketChipStageGenerator.scala)
Caused by: java.lang.ClassNotFoundException: DefaultRV32Config
at java.base/jdk.internal.loader.BuiltinClassLoader.loadClass(BuiltinClassLoader.java:581)
at java.base/jdk.internal.loader.ClassLoaders$AppClassLoader.loadClass(ClassLoaders.java:178)
at java.base/java.lang.ClassLoader.loadClass(ClassLoader.java:522)
at java.base/java.lang.Class.forName0(Native Method)
at java.base/java.lang.Class.forName(Class.java:315)
at freechips.rocketchip.util.HasRocketChipStageUtils.$anonfun$getConfig$1(GeneratorUtils.scala:16)
... 35 more
make: *** [/home/hujiyong/RISCV/rocket-chip/vsim/Makefrag-verilog:13: /home/hujiyong/RISCV/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultRV32Config.fir] Error 1
I tried reinstall the tools, but the problem still exists.
The same error happens when making with emulator, or with other configs.
I tried to use another config other than DefaultConfig when making, but was warned the following:
I tried reinstall the tools, but the problem still exists. The same error happens when making with emulator, or with other configs.