Open gonsolo opened 8 months ago
Currently the only target in the root Makefile is "verilog" (and "clean").
It would be nice to have a simple "Hello world" simulation for verilator.
Currently there are the following broken links in the root Makefile:
How should I use the Rocket chip generator? Using the cycle-accurate Verilator simulation Mapping a Rocket core down to an FPGA Pushing a Rocket core through the VLSI tools How can I parameterize my Rocket chip?
How should I use the Rocket chip generator?
Using the cycle-accurate Verilator simulation Mapping a Rocket core down to an FPGA Pushing a Rocket core through the VLSI tools
How can I parameterize my Rocket chip?
I propose the following:
Thanks g
Currently the only target in the root Makefile is "verilog" (and "clean").
It would be nice to have a simple "Hello world" simulation for verilator.
Currently there are the following broken links in the root Makefile:
I propose the following:
Thanks g