chipsalliance / rocket-chip

Rocket Chip Generator
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"Hello world" simulation target and instruction in README.md #3562

Open gonsolo opened 8 months ago

gonsolo commented 8 months ago

Currently the only target in the root Makefile is "verilog" (and "clean").

It would be nice to have a simple "Hello world" simulation for verilator.

Currently there are the following broken links in the root Makefile:

How should I use the Rocket chip generator?

Using the cycle-accurate Verilator simulation Mapping a Rocket core down to an FPGA Pushing a Rocket core through the VLSI tools

How can I parameterize my Rocket chip?

I propose the following:

  1. Add a target to the root Makefile to simulate a simple example.
  2. Mention it in the README.md
  3. Remove the broken links.

Thanks g