Unused standard parts of mie register not properly implementing read-only 0

Type of issue: bug report

What is the current behavior? The mie register is currently implemented such that it is not initialized (no issue as such). However, this leads to RTL simulation traces where the first CSR instruction accessing mie reads for example 1 from bit 0 of mie (if 1 was picked as initial value) and this bit is defined as read-only 0 in chapter 3.1.9 of the privileged specification. Any actual CSR write to mie sets the unused bits to 0 and they cannot get back to 1, so subsequent CSR accesses are sure to read 0, but the initial read is still violating the "read-only 0" requirement from the privileged specification. There may be similar issues with bit 1 in other configurations (which is additionally read-only zero in case S mode is not implemented).

What is the expected behavior? To honor the read-only zero requirement of the spec, it should be made sure that the initial CSR access to mie also returns 0 for the unused standard bits. This is handled properly for mip which has analogous read-only 0 requirements in the specification, but not for mie.

Please tell us about your environment: The issue was found with the Questa Processor app on the generated RTL of the default configuration.

chipsalliance / rocket-chip

Unused standard parts of mie register not properly implementing read-only 0 #3610