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chipsalliance / rocket-chip

Rocket Chip Generator
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Using make Config Generated Verilog with TestHarness in Vivado for Logic Synthesis #3611

Closed fengmu0124 closed 5 months ago

fengmu0124 commented 5 months ago

Can I directly use the Verilog files with 'TestHarness' generated under 'generated-src' by running make Config for logic synthesis in Vivido?

sequencer commented 5 months ago

The Rocket-Chip is target as a SoC Library, for VLSI or FPGA flow, you can refer to the Chipyard project.