Commit Description:
Change a_sublane to not count sublanes if it's a read. Reads return full data width, no matter if the A channel size is not the data width
Comments
Noticed that when size is not maxed out on a read to the TLRAM, it was translating it to a RMW. Would make sense if there was an ECC error but that should get handled by d_need_fix in d_wb, sublane should not be responsible.
Commit Description: Change a_sublane to not count sublanes if it's a read. Reads return full data width, no matter if the A channel size is not the data width
Comments Noticed that when size is not maxed out on a read to the TLRAM, it was translating it to a RMW. Would make sense if there was an ECC error but that should get handled by d_need_fix in d_wb, sublane should not be responsible.
val d_wb = d_full && (d_sublane || d_atomic || (d_read && d_need_fix))