Doing this feature as required by the architecture:
For guest-page faults, the trap instruction register is written with a special pseudoinstruction value if:
(a) the fault is caused by an implicit memory access for VS-stage address translation, and
(b) a nonzero value (the faulting guest physical address) is written to mtval2 or htval.
If both conditions are met, the value written to mtinst or htinst must be taken from the table below; zero is not allowed.
The mtinst and htinst CSRs are hardwired to 0, placing additional onus on hypervisor software to use the HLVX instruction.
Type of change: bug report | feature request
Impact: functional addition
Development Phase: implementation
Release Notes
Guest-page faults caused by an implicit memory access for VS-stage address translation write the architecturally-defined pseudo-instruction to mtinst or htinst because a nonzero value (the faulting guest physical address) is written to mtval2 or htval.
Related issue:
Doing this feature as required by the architecture:
Paying off this tech debt from https://github.com/chipsalliance/rocket-chip/pull/2841
Type of change: bug report | feature request
Impact: functional addition
Development Phase: implementation
Release Notes Guest-page faults caused by an implicit memory access for VS-stage address translation write the architecturally-defined pseudo-instruction to
mtinstorhtinstbecause a nonzero value (the faulting guest physical address) is written tomtval2orhtval.