Other information: Request optional parameter that allows override of desiredName when instantiating a ClockDomain
What is the use case for changing the behavior?: Would allow for user defined uniquifying of verilog module and file names when instantiating a clock domain. Currently, all peripheral clock domain names are autogenerated and thus not easily mapped to the underlying modules instantiated within those domains.
For example:
ClockSinkDomain.sv
ClockSinkDomain_1.sv
ClockSinkDomain_2.sv
...
jerryz123
commented
1 month ago
Type of issue: Feature Request
Impact: API Addition (no impact on existing code)
Development Phase: Request
Other information: Request optional parameter that allows override of desiredName when instantiating a ClockDomain
What is the use case for changing the behavior?: Would allow for user defined uniquifying of verilog module and file names when instantiating a clock domain. Currently, all peripheral clock domain names are autogenerated and thus not easily mapped to the underlying modules instantiated within those domains.
For example: ClockSinkDomain.sv ClockSinkDomain_1.sv ClockSinkDomain_2.sv ...