This improves the naming stability of generated verilog by adding descriptive suffixes to module names. This makes it easier to determine where many important modules are instantiated.
Related issue:
Type of change: bug report | feature request | other enhancement
Impact: no functional change | API addition (no impact on existing code) | API modification
This improves the naming stability of generated verilog by adding descriptive suffixes to module names. This makes it easier to determine where many important modules are instantiated.
Related issue:
Type of change: bug report | feature request | other enhancement
Impact: no functional change | API addition (no impact on existing code) | API modification
Development Phase: proposal | implementation
Release Notes