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Rocket Chip Generator
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Java compilation error, prompting no byte 4096 alignment #3658

Closed Jerryy959 closed 2 weeks ago

Jerryy959 commented 1 month ago

Everything went wrong when I added support for hypervisor extensions to my configuration file. This error was prompted截屏2024-07-26 04 25 23

My configuration file looks like this：

package freechips.rocketchip.uintr

import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.tile._
import freechips.rocketchip.devices.tilelink._

class WithCustomBootROM(resetAddress: BigInt, bootImgPath: String)
  extends Config((_, _, up) => { case BootROMLocated(x) =>
    up(BootROMLocated(x)).map(_.copy(hang = resetAddress, contentFileName = bootImgPath))
  })

class WithUIPI extends Config((_, _, _) => {
  case BuildRoCC => Seq((p: Parameters) => {
    val module = LazyModule(new UIPI(OpcodeSet.custom3)(p))
    module
  })
})

class UintrConfig extends Config(
  new WithHypervisor ++
  new WithNBigCores(4) ++
    new WithNExtTopInterrupts(6) ++
    new WithTimebase((BigInt(10000000))) ++ // 10 MHz
    new WithDTS("freechips.rocketchip-unknown", Nil) ++
    new WithUIPI ++
    new WithCustomBootROM(0x10000, "../common/boot/bootrom/bootrom.img") ++
    new WithDefaultMemPort ++
    new WithDefaultMMIOPort ++
    new WithoutTLMonitors ++
    new WithCoherentBusTopology ++
    new BaseSubsystemConfig
)

class UintrTestConfig extends Config(new DefaultConfig ++ new WithUIPI)

The entire error message is：

[success] Total time: 71 s (01:11), completed Jul 26, 2024 4:18:29 AM mkdir -p /home/jerry/bitstream/uintr-rocket-chip/rocket-chip/emulator/generated-src/ cd /home/jerry/bitstream/uintr-rocket-chip/rocket-chip && java -Xmx2G -Xss8M -cp /home/jerry/bitstream/uintr-rocket-chip/rocket-chip/rocketchip.jar freechips.rocketchip.uintr.Generator -td /home/jerry/bitstream/uintr-rocket-chip/rocket-chip/emulator/generated-src -T freechips.rocketchip.uintr.Top -C freechips.rocketchip.uintr.UintrConfig Init BootROM 65536 ../common/boot/bootrom/bootrom.img Exception in thread "main" java.lang.reflect.InvocationTargetException at ... () at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36) at ... () at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace) Caused by: java.lang.IllegalArgumentException: requirement failed: All memory regions must be 4096-byte aligned at scala.Predef$.require(Predef.scala:281) at freechips.rocketchip.rocket.PTW.$anonfun$new$218(PTW.scala:378) at freechips.rocketchip.rocket.PTW.$anonfun$new$218$adapted(PTW.scala:375) at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:286) at scala.collection.immutable.Range.foreach(Range.scala:158) at scala.collection.TraversableLike.map(TraversableLike.scala:286) at scala.collection.TraversableLike.map$(TraversableLike.scala:279) at scala.collection.AbstractTraversable.map(Traversable.scala:108) at freechips.rocketchip.rocket.PTW.$anonfun$new$217(PTW.scala:375) at chisel3.internal.prefix$.apply(prefix.scala:48) at freechips.rocketchip.rocket.PTW.$anonfun$new$216(PTW.scala:117) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.rocket.PTW.$anonfun$new$4(PTW.scala:117) at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23) at chisel3.withClock$.apply(MultiClock.scala:47) at freechips.rocketchip.rocket.PTW.(PTW.scala:140) at freechips.rocketchip.rocket.CanHavePTWModule.$anonfun$ptw$2(PTW.scala:616) at chisel3.Module$.do_apply(Module.scala:53) at freechips.rocketchip.rocket.CanHavePTWModule.$anonfun$ptw$1(PTW.scala:616) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.rocket.CanHavePTWModule.$init$(PTW.scala:616) at freechips.rocketchip.tile.RocketTileModuleImp.(RocketTile.scala:122) at freechips.rocketchip.tile.RocketTile.$anonfun$module$1(RocketTile.scala:105) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.tile.RocketTile.module$lzycompute(RocketTile.scala:105) at freechips.rocketchip.tile.RocketTile.module(RocketTile.scala:105) at freechips.rocketchip.tile.RocketTile.module(RocketTile.scala:38) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$3(LazyModule.scala:278) at chisel3.Module$.do_apply(Module.scala:53) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$2(LazyModule.scala:278) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:278) at scala.collection.immutable.List.flatMap(List.scala:366) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:276) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:273) at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:344) at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$22$2(LazyModule.scala:357) at chisel3.withClockAndReset$.apply(MultiClock.scala:26) at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$22$1(LazyModule.scala:357) at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48) at freechips.rocketchip.diplomacy.LazyRawModuleImp.(LazyModule.scala:356) at freechips.rocketchip.prci.Domain$$anon$1.(ClockDomain.scala:10) at freechips.rocketchip.prci.Domain.$anonfun$module$1(ClockDomain.scala:10) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.prci.Domain.module$lzycompute(ClockDomain.scala:10) at freechips.rocketchip.prci.Domain.module(ClockDomain.scala:10) at freechips.rocketchip.prci.Domain.module(ClockDomain.scala:7) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$3(LazyModule.scala:278) at chisel3.Module$.do_apply(Module.scala:53) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$2(LazyModule.scala:278) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:278) at scala.collection.immutable.List.flatMap(List.scala:366) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:276) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:273) at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:344) at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$22$2(LazyModule.scala:357) at chisel3.withClockAndReset$.apply(MultiClock.scala:26) at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$22$1(LazyModule.scala:357) at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48) at freechips.rocketchip.diplomacy.LazyRawModuleImp.(LazyModule.scala:356) at freechips.rocketchip.prci.Domain$$anon$1.(ClockDomain.scala:10) at freechips.rocketchip.prci.Domain.$anonfun$module$1(ClockDomain.scala:10) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.prci.Domain.module$lzycompute(ClockDomain.scala:10) at freechips.rocketchip.prci.Domain.module(ClockDomain.scala:10) at freechips.rocketchip.prci.Domain.module(ClockDomain.scala:7) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$3(LazyModule.scala:278) at chisel3.Module$.do_apply(Module.scala:53) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$2(LazyModule.scala:278) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$1(LazyModule.scala:278) at scala.collection.immutable.List.flatMap(List.scala:366) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:276) at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:273) at freechips.rocketchip.diplomacy.LazyModuleImp.instantiate(LazyModule.scala:335) at freechips.rocketchip.diplomacy.LazyModuleImp.$anonfun$x$21$1(LazyModule.scala:337) at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48) at freechips.rocketchip.diplomacy.LazyModuleImp.(LazyModule.scala:337) at freechips.rocketchip.subsystem.BareSubsystemModuleImp.(BaseSubsystem.scala:29) at freechips.rocketchip.subsystem.BaseSubsystemModuleImp.(BaseSubsystem.scala:122) at freechips.rocketchip.subsystem.RocketSubsystemModuleImp.(RocketSubsystem.scala:40) at freechips.rocketchip.uintr.FPGAZynqTopModuleImp.(Top.scala:65) at freechips.rocketchip.uintr.FPGAZynqTop.$anonfun$module$1(Top.scala:62) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.uintr.FPGAZynqTop.module$lzycompute(Top.scala:62) at freechips.rocketchip.uintr.FPGAZynqTop.module(Top.scala:62) at freechips.rocketchip.uintr.Top.$anonfun$target$2(Top.scala:14) at chisel3.Module$.do_apply(Module.scala:53) at freechips.rocketchip.uintr.Top.$anonfun$target$1(Top.scala:14) at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) at freechips.rocketchip.uintr.Top.(Top.scala:14) at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method) at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62) at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45) at java.lang.reflect.Constructor.newInstance(Constructor.java:423) at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:36) at chisel3.Module$.do_apply(Module.scala:53) at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:33) at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:720) at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62) at chisel3.internal.Builder$.build(Builder.scala:715) at chisel3.stage.phases.Elaborate.$anonfun$transform$1(Elaborate.scala:33) at scala.collection.TraversableLike.$anonfun$flatMap$1(TraversableLike.scala:293) at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62) at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55) at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49) at scala.collection.TraversableLike.flatMap(TraversableLike.scala:293) at scala.collection.TraversableLike.flatMap$(TraversableLike.scala:290) at scala.collection.AbstractTraversable.flatMap(Traversable.scala:108) at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:28) at chisel3.stage.phases.Elaborate.transform(Elaborate.scala:21) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15) at firrtl.options.Translator.transform(Phase.scala:248) at firrtl.options.Translator.transform$(Phase.scala:248) at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15) at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280) at firrtl.Utils$.time(Utils.scala:181) at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280) at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126) at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122) at scala.collection.immutable.List.foldLeft(List.scala:91) at firrtl.options.DependencyManager.transform(DependencyManager.scala:269) at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255) at firrtl.options.PhaseManager.transform(DependencyManager.scala:443) at chisel3.stage.ChiselStage.run(ChiselStage.scala:45) at firrtl.options.Stage$$anon$1.transform(Stage.scala:43) at firrtl.options.Stage$$anon$1.transform(Stage.scala:43) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15) at firrtl.options.Translator.transform(Phase.scala:248) at firrtl.options.Translator.transform$(Phase.scala:248) at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15) at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47) at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126) at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122) at scala.collection.immutable.List.foldLeft(List.scala:91) at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47) at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137) at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62) at logger.Logger$.makeScope(Logger.scala:135) at firrtl.options.Stage.transform(Stage.scala:47) at firrtl.options.Stage.transform(Stage.scala:17) at firrtl.options.DependencyManager.$anonfun$transform$5(DependencyManager.scala:280) at firrtl.Utils$.time(Utils.scala:181) at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:280) at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126) at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122) at scala.collection.immutable.List.foldLeft(List.scala:91) at firrtl.options.DependencyManager.transform(DependencyManager.scala:269) at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255) at firrtl.options.PhaseManager.transform(DependencyManager.scala:443) at freechips.rocketchip.system.RocketChipStage.run(RocketChipStageGenerator.scala:44) at firrtl.options.Stage$$anon$1.transform(Stage.scala:43) at firrtl.options.Stage$$anon$1.transform(Stage.scala:43) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38) at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15) at firrtl.options.Translator.transform(Phase.scala:248) at firrtl.options.Translator.transform$(Phase.scala:248) at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15) at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47) at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126) at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122) at scala.collection.immutable.List.foldLeft(List.scala:91) at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47) at logger.Logger$.$anonfun$makeScope$2(Logger.scala:137) at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62) at logger.Logger$.makeScope(Logger.scala:135) at firrtl.options.Stage.transform(Stage.scala:47) at firrtl.options.Stage.execute(Stage.scala:58) at firrtl.options.StageMain.main(Stage.scala:71) at freechips.rocketchip.uintr.Generator.main(Generator.scala) make[1]: [Makefrag-verilator:13: /home/jerry/bitstream/uintr-rocket-chip/rocket-chip/emulator/generated-src/freechips.rocketchip.uintr.UintrConfig.fir] Error 1 make[1]: Leaving directory '/home/jerry/bitstream/uintr-rocket-chip/rocket-chip/emulator' make: [../common/Makefrag:44: /home/jerry/bitstream/uintr-rocket-chip/rocket-chip/emulator/generated-src/freechips.rocketchip.uintr.UintrConfig.v] Error 2

How can i solve this?

Jerryy959 commented 1 month ago

I found the error come from here:

https://github.com/U-interrupt/rocket-chip/blob/2a66519752149804d9e0bad99326ee51687b70fa/src/main/scala/rocket/PTW.scala#L375C1-L383C4

do you have any ideas?

jerryz123 commented 1 month ago

The error message is descriptive: All memory regions must be 4096-byte aligned at scala.Predef$.require(Predef.scala:281)

Jerryy959 commented 1 month ago

This error only occurs when I turn on support for hypervisor extensions.

Jerryy959 commented 2 weeks ago

Check this issue to track my solution, this can be closed. https://github.com/BOSC-Hvisor/hvisor-rocket-chip/issues/3