Where to find systemverilog code for AXI slave with DDR memory controller?

[davidfongsj1108]

Hi,

I was able to generate the verilog for the rocketchip.

However, I saw there is an AXI like interface "iomem*". Is there systemverilog code that takes the AXI -like master signals from Top and drives an AXI slave with DDR memory controller?

Thanks,

David

[zhemao]

For our FPGA flow, we use the AXI DDR memory controllers provided by Xilinx. For our taped out chips, we use the backup memory.

If you are using a different FPGA architecture or silicon technology, you'll have to find your own memory controller.

[davidfongsj1108]

Please explain "backup memory" for the taped out chips.

[colinschmidt]

"backup memory" is a slow digital IO that uses a non-standard (ucb-bar specific) format

[davidfongsj1108]

Ok. Please close this issue.