I want to make verilog DefaultFPGAConfig and I get the following error. Could anyone please tell me why I'm getting this error ?
Also, I want to make verilog for the zedboard, should I use DefaultSmallFPGAConfig ?
Thank you
alpha@alpha-VirtualBox:~/fpga-zynq/rocket-chip/vsim$ make verilog CONFIG=DefaultFPGAConfig
mkdir -p /home/alpha/fpga-zynq/rocket-chip/vsim/generated-src/
cd /home/alpha/fpga-zynq/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar /home/alpha/fpga-zynq/rocket-chip/sbt-launch.jar "run-main rocketchip.Generator /home/alpha/fpga-zynq/rocket-chip/vsim/generated-src rocketchip TestHarness rocketchip DefaultFPGAConfig"
[info] Loading project definition from /home/alpha/fpga-zynq/rocket-chip/project
Using addons:
[info] Set current project to rocketchip (in build file:/home/alpha/fpga-zynq/rocket-chip/)
[info] Compiling 1 Scala source to /home/alpha/fpga-zynq/rocket-chip/chisel3/target/scala-2.11/classes...
[info] Packaging /home/alpha/fpga-zynq/rocket-chip/chisel3/target/scala-2.11/chisel3_2.11-3.1-SNAPSHOT.jar ...
[info] Done packaging.
[info] Running rocketchip.Generator /home/alpha/fpga-zynq/rocket-chip/vsim/generated-src rocketchip TestHarness rocketchip DefaultFPGAConfig
[info] [0.004] Elaborating design...
[error] (run-main-0) java.lang.reflect.InvocationTargetException
java.lang.reflect.InvocationTargetException
at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:57)
at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
at java.lang.reflect.Constructor.newInstance(Constructor.java:526)
at util.HasGeneratorUtilities$$anonfun$2.apply(GeneratorUtils.scala:47)
at util.HasGeneratorUtilities$$anonfun$2.apply(GeneratorUtils.scala:44)
at chisel3.core.Module$.do_apply(Module.scala:42)
at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:92)
at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:240)
at chisel3.internal.Builder$$anonfun$build$1.apply(Builder.scala:238)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:58)
at chisel3.internal.Builder$.build(Builder.scala:238)
at chisel3.Driver$.elaborate(Driver.scala:92)
Caused by: java.lang.IllegalArgumentException: requirement failed
at scala.Predef$.require(Predef.scala:207)
at chisel3.core.Vec$.do_apply(Aggregate.scala:70)
at chisel3.core.Vec$.do_fill(Aggregate.scala:132)
at uncore.devices.TLDebugModuleOuter$$anon$4.<init>(Debug.scala:350)
at uncore.devices.TLDebugModuleOuter.module$lzycompute(Debug.scala:291)
at uncore.devices.TLDebugModuleOuter.module(Debug.scala:291)
at diplomacy.LazyModule$$anonfun$instantiate$1$$anonfun$apply$5.apply(LazyModule.scala:60)
at diplomacy.LazyModule$$anonfun$instantiate$1$$anonfun$apply$5.apply(LazyModule.scala:60)
at chisel3.core.Module$.do_apply(Module.scala:42)
at diplomacy.LazyModule$$anonfun$instantiate$1.apply(LazyModule.scala:60)
at diplomacy.LazyModule$$anonfun$instantiate$1.apply(LazyModule.scala:57)
at scala.collection.immutable.List.foreach(List.scala:381)
at diplomacy.LazyModule.instantiate(LazyModule.scala:57)
at diplomacy.LazyModuleImp.<init>(LazyModule.scala:151)
java.lang.RuntimeException: Nonzero exit code: 1
at scala.sys.package$.error(package.scala:27)
at sbt.BuildCommon$$anonfun$toError$1.apply(Defaults.scala:2081)
at sbt.BuildCommon$$anonfun$toError$1.apply(Defaults.scala:2081)
at scala.Option.foreach(Option.scala:236)
at sbt.BuildCommon$class.toError(Defaults.scala:2081)
at sbt.Defaults$.toError(Defaults.scala:39)
at sbt.Defaults$$anonfun$runMainTask$1$$anonfun$apply$36$$anonfun$apply$37.apply(Defaults.scala:740)
at sbt.Defaults$$anonfun$runMainTask$1$$anonfun$apply$36$$anonfun$apply$37.apply(Defaults.scala:738)
at scala.Function1$$anonfun$compose$1.apply(Function1.scala:47)
at sbt.$tilde$greater$$anonfun$$u2219$1.apply(TypeFunctions.scala:40)
at sbt.std.Transform$$anon$4.work(System.scala:63)
at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:228)
at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:228)
at sbt.ErrorHandling$.wideConvert(ErrorHandling.scala:17)
[error] (rocketchip/compile:runMain) Nonzero exit code: 1
[error] Total time: 19 s, completed May 22, 2017 9:30:22 PM
make: *** [/home/alpha/fpga-zynq/rocket-chip/vsim/generated-src/rocketchip.DefaultFPGAConfig.fir] Error 1
Hello,
I want to make verilog DefaultFPGAConfig and I get the following error. Could anyone please tell me why I'm getting this error ? Also, I want to make verilog for the zedboard, should I use DefaultSmallFPGAConfig ?
Thank you