DualChannelConfig is broken

[zhemao]

I've been trying to instantiate dual-memory channel configurations, but I get Chisel elaboration errors. At first I get

java.lang.IllegalArgumentException: requirement failed: minAlignment (64) must be >= maxTransfer (256)
    at scala.Predef$.require(Predef.scala:219)
    at uncore.axi4.AXI4SlaveParameters.<init>(Parameters.scala:29)
    at rocketchip.HasPeripheryMasterAXI4MemPort$$anonfun$3.apply(Periphery.scala:138)

So I fixed that with the following change in HasPeripheryMasterAXI4MemPort

-        supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
-        supportsRead  = TransferSizes(1, 256),
+        supportsWrite = TransferSizes(1, blockBytes),
+        supportsRead  = TransferSizes(1, blockBytes),

But after that I now get this error

java.lang.IllegalArgumentException: requirement failed
    at scala.Predef$.require(Predef.scala:207)
    at uncore.devices.TLROM$$anon$1.<init>(Rom.scala:34)

This is from the following line

val contents = contentsDelayed
val wrapSize = 1 << log2Ceil(contents.size)
require (wrapSize <= size)

Printing out the value of contents.size indicates that it's 4196620. So somehow increasing the number of memory channels causes the DTB to balloon to >4MB? I don't understand why that happens.

[terpstra]

Oh. I understand why that happened. DTS can only describe memory regions that are contiguous. So when you have controllers with alternating cache blocks it will describe every single block alternating between the two controllers!

The solution is to describe both channels as the same DTS device.

[zhemao]

Yeah, that's what I thought. But how do I change HasPeripheryMasterAXI4MemPort trait to fix it? I suspect the change will have to be made somewhere deep in AXI4BlindOutputNode.