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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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SweRV RISC-V: incomplete headers, no header guards + wrong compile order #315

Closed Nic30 closed 3 years ago

Nic30 commented 5 years ago

Hello,

SweRV RISC-V files do have problems mentioned in topic. The code is working actually, but correct compile order has to be specified. Namely preprocessor can be called only for a specific files and not for all files like it is happening now as all files are in file list.

I am not sure if tools should try to solve this problem, or the test is wrong. What do you think?

hzeller commented 3 years ago

And currently a file is referenced that can't be opened - which all tools complain about in their respective ways (third_party/cores/swerv/configs/snapshots/default/common_defines.vh).

Time for #998 ...

joannabrozek commented 3 years ago

Fixed in #1300, #1341 and #1344.