chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/tools/verilator from `3d57256` to `a30930b` #5756

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/tools/verilator from 3d57256 to a30930b.

Commits
  • a30930b Fix unsound temporary name generation in V3DfgRegularize
  • 3a1355f Fix bad assertion in DFG variable elimination
  • 97db128 Tests: Add VPI dump testcases (#4838)
  • See full diff in compare view


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github-actions[bot] commented 3 months ago

Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
tree_sitter_verilog 0 0 0 0 4499
SynligYosys 1 0 0 0 4310
sv_parser 0 0 0 0 4590
Yosys 0 1 0 0 4311
Sv2v_zachjs 0 0 0 0 4653
moore_parse 0 0 0 0 4499
Verible 0 0 0 0 4499
Slang 0 0 0 0 4653
Icarus 0 0 0 0 4668
UhdmVerilator 0 0 0 0 4668
moore 0 0 0 0 4590
Surelog 0 0 0 0 4653
Slang_parse 0 0 0 0 4590
Odin 0 0 0 0 4590
Verilator 0 7 0 0 4661
VeribleExtractor 0 0 0 0 4499
yosys_slang 0 0 0 0 3849

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