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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/opentitan from `eec48c4` to `62abbba` #5767

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/cores/opentitan from eec48c4 to 62abbba.

Commits
  • 62abbba [rom] Add ECDSA P256 support to manifest.h
  • dd041b9 [dv,otp_ctrl] Fix issues related to random resets
  • 4c06f37 [adc_ctrl] Updates to LP -> NP transition
  • 9d8cc48 [adc_ctrl] Add FSM state observation register for debug purposes
  • 1d8f192 [adc_ctrl] Fix low-power sampling mode
  • 3ab37e4 [adc_ctrl] Bump version to 2.0.0
  • ce4c06f [sival,aes] Clarify purpose of chip_sw_aes_masking_off test
  • 4e422bd [entropy_src/dv] Test whether noise source symbols are not dropped
  • 0c580fa [uart] Further limit baud in uart_rx_oversample
  • b6eb0fc [usbdev] Remove test of usbdev pin-flipping from SiVal
  • Additional commits viewable in compare view


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dependabot[bot] commented 3 months ago

Superseded by #5777.