chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/black-parrot from `c0a071d` to `b53f899` #5772

Closed dependabot[bot] closed 6 months ago

dependabot[bot] commented 6 months ago

Bumps third_party/cores/black-parrot from c0a071d to b53f899.

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github-actions[bot] commented 6 months ago

Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
tree_sitter_verilog 0 0 0 0 4499
SynligYosys 0 0 0 0 4311
Verilator 0 0 0 0 4668
Yosys 0 1 0 0 4311
moore 0 0 0 0 4590
Slang 0 0 0 0 4653
VeribleExtractor 0 0 0 0 4499
yosys_slang 0 0 0 0 3849
Surelog 0 0 0 0 4653
Sv2v_zachjs 0 0 0 0 4653
moore_parse 0 0 0 0 4499
UhdmVerilator 0 0 0 0 4668
Odin 0 0 0 0 4590
sv_parser 0 0 0 0 4590
Verible 0 0 0 0 4499
Icarus 0 0 0 0 4668
Slang_parse 0 0 0 0 4590

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