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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/opentitan from `eec48c4` to `d7a0846` #5781

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/cores/opentitan from eec48c4 to d7a0846.

Commits
  • d7a0846 [rom_e2e] fix ROM e2e test after removing 64k slot size limit
  • c5df47c [rom_e2e] add e2e test for big ROM_EXT images
  • 5e7c1ab [rom] remove 64k code size restriction ROM_EXT
  • 53709bf [adc_ctrl/doc] Minor tweak
  • 8b7a0ea [dv,usbdev] Test plan additions for V1
  • c213a8a [dv] Fix more timeout comments with wrong units
  • 86b94a2 [usbdev,dv] Tighten constraint on AON clock frequency
  • 51fc76c [uart] Speed up uart_intr test
  • b2cb0bb [usbdev,dv] Drop unnecessary calls to csr_update
  • 16d0013 [usbdev,dv] Get rid of rand_or_not class variable from vseqs
  • Additional commits viewable in compare view


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dependabot[bot] commented 3 months ago

Superseded by #5789.