chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/tools/zachjs-sv2v from `9825bb9` to `df01650` #5785

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/tools/zachjs-sv2v from 9825bb9 to df01650.

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github-actions[bot] commented 3 months ago

Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
Sv2v_zachjs 0 0 0 0 4653
Odin 0 0 0 0 4590
Slang 0 0 0 0 4653
sv_parser 0 0 0 0 4590
moore 0 0 0 0 4590
UhdmVerilator 0 0 0 0 4668
Verilator 0 0 0 0 4668
Icarus 0 0 0 0 4668
Verible 0 0 0 0 4499
moore_parse 0 0 0 0 4499
SynligYosys 0 0 0 0 4311
VeribleExtractor 0 0 0 0 4499
Slang_parse 0 0 0 0 4590
Surelog 0 0 0 0 4653
Yosys 0 0 0 0 4312
tree_sitter_verilog 0 0 0 0 4499
yosys_slang 0 0 0 0 3849

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