chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/tools/yosys from `6d528ef` to `0909c2e` #5786

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/tools/yosys from 6d528ef to 0909c2e.

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github-actions[bot] commented 3 months ago

Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
tree_sitter_verilog 0 0 0 0 4499
Yosys 0 0 0 0 4312
Verilator 0 0 0 0 4668
UhdmVerilator 0 0 0 0 4668
Verible 0 0 0 0 4499
Slang 0 0 0 0 4653
yosys_slang 0 0 0 0 3849
Odin 0 0 0 0 4590
moore 0 0 0 0 4590
Slang_parse 0 0 0 0 4590
SynligYosys 0 1 0 0 4310
VeribleExtractor 0 0 0 0 4499
Surelog 0 0 0 0 4653
Icarus 0 0 0 0 4668
Sv2v_zachjs 0 0 0 0 4653
sv_parser 0 0 0 0 4590
moore_parse 0 0 0 0 4499

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