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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/tools/verible from `46de0f6` to `4f98e14` #5787

Open dependabot[bot] opened 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/tools/verible from 46de0f6 to 4f98e14.

Commits
  • 4f98e14 Merge pull request #2141 from corco/update-ci-windows-2022
  • f1242ff Updated Windows to 2022 in CI
  • 01e332e Merge pull request #2137 from hzeller/feature-20240308-explicit-zlib
  • 5612f80 Merge pull request #2138 from hzeller/feature-20240308-remove-stray-py
  • 4546210 Remove some stray Python third_party/, not needed anymore.
  • 8883813 Since we use zlib, don't rely on protobuf implicitly providing it.
  • d9163ae Merge pull request #2135 from hzeller/feature-20240307-fix-deps
  • df1e065 Merge pull request #2134 from hzeller/feature-20240307-jcxxgen-to-lsp
  • 29f2eed Fix some dependencies.
  • 902ee90 Don't wrap json generation in jcxxgen() macro, use genrule directly.
  • See full diff in compare view


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