chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/black-parrot from `b53f899` to `fc197c5` #5792

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/cores/black-parrot from b53f899 to fc197c5.

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github-actions[bot] commented 3 months ago

Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
SynligYosys 0 0 0 0 4311
moore_parse 0 0 0 0 4499
tree_sitter_verilog 0 0 0 0 4499
Slang 0 0 0 0 4653
Icarus 0 0 0 0 4668
Surelog 0 0 0 0 4653
UhdmVerilator 0 0 0 0 4668
Yosys 0 0 0 0 4312
VeribleExtractor 0 0 0 0 4499
Verilator 0 0 0 0 4668
Odin 0 0 0 0 4590
Sv2v_zachjs 0 0 0 0 4653
Verible 0 0 0 0 4499
moore 0 0 0 0 4590
yosys_slang 0 0 0 0 3849
sv_parser 0 0 0 0 4590
Slang_parse 0 0 0 0 4590

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