chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
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UVM-related tests come with undefined package's import #5798

Open ssmolov opened 3 months ago

ssmolov commented 3 months ago

About 140 tests from chapter-16 and chapter-18 subdirectories start from importing the uvm_pkg package before it's definition. The include directive comes right after the import:

import uvm_pkg::*;
`include "uvm_macros.svh"

Both open-source (slang) and commercial (VCS) EDA tools report errors on such tests -- are these tests treated to be negative? Here is a fragment of VCS log for chapter-16/16.2--assert-final-uvm.sv test:

Parsing design file '16.2--assert-final-uvm.sv'

Error-[SV-LCM-PND] Package not defined
16.2--assert-final-uvm.sv, 19
$unit, "uvm_pkg::"
  Package scope resolution failed. Token 'uvm_pkg' is not a package. 
  Originating module '$unit'.
  Move package definition before the use of the package.

Here is the complete list of such tests: undefined-import-uvm-tests.txt

jcurtiss8086 commented 3 months ago

uvm_macros.svh is not what contains the definition of uvm_pkg. As the name implies, this svh file only contains `define statements for various helper macros, e.g. `uvm_info, `uvm_error

uvm_pkg.sv is a separate file that must be a part of the filelist in addition to the test-case file.

It does appear that the test-case in the repo is attempting to add the file to the command line. With git clone --recursive I do see that the surelog repo has the UVM directory shown below, but I suspect it is the relative hierarchies that are causing the files to not be found when being passed to other tools such as slang.

third_party/tools/Surelog/third_party/tests/Google/batch.txt
383:-cd chapter-16 -I../../../UVM/1800.2-2017-1.0/src/ ../../../UVM/1800.2-2017-1.0/src//uvm_pkg.sv -parse -nonote -noinfo -nouhdm -timescale=1ns/1ns 16.2--assert-final-uvm.sv -l 16.2--assert-final-uvm.sv.log