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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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RgGen core is broken #5800

Closed MikePopoloski closed 3 months ago

MikePopoloski commented 6 months ago

Failing in all tools that do elaboration (slang, verilator) with errors like:

../../../tests/generated/rggen/rggen.sv:156:5: error: interface port 'register_17_bus_if' not connected
  ) u_block_0 (
    ^
../../../third_party/cores/rggen-sample/block_0.sv:151:23: note: declared here
  rggen_bus_if.master register_17_bus_if
                      ^
../../../tests/generated/rggen/rggen.sv:170:6: error: port 'i_register_2_bit_field_2_latch' does not exist in 'block_0'
    .i_register_2_bit_field_2_latch             (register_2_bit_field_2_latch             ),
     ^
../../../tests/generated/rggen/rggen.sv:190:6: error: port 'i_register_5_bit_field_2' does not exist in 'block_0'
    .i_register_5_bit_field_2                   (register_5_bit_field_2[0]                ),
     ^

If a test is flat out broken for a long time it seems like it should either be fixed up or removed from the test suite.

taichi-ishitani commented 3 months ago

RgGen's sample RTL has been updated. I will fix it.