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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
297 stars 75 forks source link

build(deps): bump third_party/tools/odin_ii from `f669015` to `113655f` #6406

Closed dependabot[bot] closed 4 days ago

dependabot[bot] commented 6 days ago

Bumps third_party/tools/odin_ii from f669015 to 113655f.

Commits
  • 113655f Merge pull request #2807 from verilog-to-routing/fix-flat-sync
  • 93eed6a avoid name conflicts in sync_netlists_to_routing_flat
  • b6094d4 Merge pull request #2765 from AlexandreSinger/feature-ap-partial-legalizer-up...
  • 499b266 [AP] Partial Legalizer
  • 5a062ba Merge pull request #2802 from AlexandreSinger/feature-verify-placement
  • fdf6d3c Merge pull request #2799 from verilog-to-routing/temp_chan_w_factors_prefix_sum
  • db3f7ae fix the remaining failure in strong tests
  • dbe9903 update golden results
  • 044148b update golden results for strong tests
  • 1d4c4d6 update basic golden results
  • Additional commits viewable in compare view


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dependabot[bot] commented 4 days ago

Superseded by #6424.