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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
297 stars 75 forks source link

build(deps): bump third_party/tools/verilator-uhdm from `012ce2f` to `833c215` #6407

Closed dependabot[bot] closed 3 days ago

dependabot[bot] commented 6 days ago

Bumps third_party/tools/verilator-uhdm from 012ce2f to 833c215.

Commits
  • 833c215 Tests: Move uvm to subdirectory and add context-sensitive waivers
  • 4d95f6f Add --waiver-multiline for context-sensitive --waiver-output.
  • 46a5f04 Internals: Link 'std' in LinkFind
  • 3c686d0 Commentary
  • 7c8ff1d Add --no-std-package as subset-alias of --no-std.
  • 151c5b6 Tests: Rename some tests
  • 15d1751 Internals: Defer class extends resolution until link
  • b71d49e Internals: Defer $unit package resolution until link
  • c3b2bfb Internals: Fix missing cleanFileline
  • b74a8f1 Apply 'make format'
  • Additional commits viewable in compare view


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dependabot[bot] commented 3 days ago

Superseded by #6442.