chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/ariane from `4619a67` to `7eb59c3` #6408

Closed dependabot[bot] closed 6 days ago

dependabot[bot] commented 6 days ago

Bumps third_party/cores/ariane from 4619a67 to 7eb59c3.

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github-actions[bot] commented 6 days ago

Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
UhdmVerilator 0 0 0 0 4668
Yosys 2 1 0 0 4309
Slang_parse 0 0 0 0 4590
Surelog 0 0 0 0 4653
tree_sitter_verilog 0 0 0 0 4499
SynligYosys 0 0 0 0 4311
circt_verilog 0 0 0 0 4643
Slang 0 0 0 0 4653
yosys_slang 0 0 0 0 3850
moore 0 0 0 0 4590
VeribleExtractor 0 0 0 0 4499
Icarus 0 0 0 0 4668
moore_parse 0 0 0 0 4499
Sv2v_zachjs 0 0 0 0 4653
Odin 0 0 0 0 4590
Verilator 1 0 0 0 4667
sv_parser 0 0 0 0 4590
tree_sitter_systemverilog 0 0 0 0 4495
Verible 0 0 0 0 4499

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