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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/opentitan from `eec48c4` to `8b0e52b` #6409

Closed dependabot[bot] closed 5 days ago

dependabot[bot] commented 6 days ago

Bumps third_party/cores/opentitan from eec48c4 to 8b0e52b.

Commits
  • 8b0e52b [hw,pinmux,rtl] Make HW strap sampling and TAP muxing an ipgen param
  • c6edcb5 [hw,pinmux,rtl] Make USB wakeup an ipgen parameter
  • 32d5ae5 [ci] move GitHub runner to Ubuntu 22.04
  • 7df1a01 [prim] Exclude mem init dynamic if from synthesis
  • a430c0b [pwm,dv] Add a pwm_heartbeat_wrap test to see heartbeat wrapping
  • accbc1e [dv] Exclude some secded generation modules from coverage
  • 384cf5b [pwm,rtl] Recode a write-enable in pwm_core.sv
  • 12904b6 [hw,dma,dv] Support for Status-type interrupts
  • e2b0ef4 [hw,dma,rtl] Use a status interrupt and interrupt prims
  • 4d92d22 [hw,dma,rtl] Add STATUS.chunk_done bit
  • Additional commits viewable in compare view


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dependabot[bot] commented 5 days ago

Superseded by #6418.