chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/opentitan from `eec48c4` to `6c87274` #6434

Closed dependabot[bot] closed 8 hours ago

dependabot[bot] commented 3 days ago

Bumps third_party/cores/opentitan from eec48c4 to 6c87274.

Commits
  • 6c87274 [cryptotest] Remove redundant SHAKE testvectors
  • c119b8c [cryptotest] Add missing CSHAKE sample test vectors
  • 299a18c [cryptotest] Add CSHAKE NIST example values to KAT tests
  • 2e4474a [cryptotest] Remove redundant SHA3 testvectors
  • 9dc6779 [cryptotest] Remove dependence on vendored AES KAT test vectors
  • aac7744 [cryptotest] Add AES KAT vector to documentation
  • 9f5f9cb [otp] decouple CREATOR_SW_CFG_MANUF_STATE from SKU
  • 7afd856 [bazel,otp] update manifest with immutable ROM_EXT hash
  • dce9ae5 [otp] refactor immutable ROM_EXT otp gen tooling
  • dd94c44 [sival] Fix NA stage for crypto tests
  • Additional commits viewable in compare view


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dependabot[bot] commented 8 hours ago

Superseded by #6451.