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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/veer-el2 from `56212c4` to `3085254` #6436

Closed dependabot[bot] closed 3 days ago

dependabot[bot] commented 3 days ago

Bumps third_party/cores/veer-el2 from 56212c4 to 3085254.

Commits
  • 3085254 Merge pull request #252 from chipsalliance/kiryk/fix-custom-runs
  • 1a7a94a Merge pull request #248 from chipsalliance/wsip/icache_debug
  • a144823 Fix condition for custom tests
  • 56bbccf access icache registers in openocd test
  • 854daa3 openocd: reduce verbosity
  • See full diff in compare view


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github-actions[bot] commented 3 days ago

Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
Odin 0 0 0 0 4585
moore 0 0 0 0 4585
Slang_parse 0 0 0 0 4585
Icarus 0 0 0 0 4663
moore_parse 0 0 0 0 4494
tree_sitter_verilog 0 0 0 0 4494
VeribleExtractor 0 0 0 0 4494
SynligYosys 0 0 0 0 4306
Yosys 0 0 0 0 4307
UhdmVerilator 0 0 0 0 4663
Surelog 0 0 0 0 4648
sv_parser 0 0 0 0 4585
Verilator 0 0 0 0 4663
Verible 0 0 0 0 4494
Sv2v_zachjs 0 0 0 0 4648
yosys_slang 0 0 0 0 3845
tree_sitter_systemverilog 0 0 0 0 4490
circt_verilog 0 0 0 0 4638
Slang 0 0 0 0 4648

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