chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/tools/circt-verilog from `2cdde17` to `2fd0b29` #6439

Closed dependabot[bot] closed 3 days ago

dependabot[bot] commented 3 days ago

Bumps third_party/tools/circt-verilog from 2cdde17 to 2fd0b29.

Commits
  • 2fd0b29 [FIRRTL] Refactor class lowering to avoid unnecessary cloning (#7823)
  • 2d93ce7 Dedup: hash modules back->front (#7820)
  • ac249e5 [MemoryBanking] Fix bad includes in MemoryBanking
  • a40aed0 [Handshake] Adding func instance op for integration (#7812)
  • 0122bad [FIRRTL] Accept list of parameters for formal construct (#7813)
  • 8c966c1 [FIRRTL] GCT Cleanup, NFC
  • See full diff in compare view


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