chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/ariane from `33c5d77` to `e7f27c1` #6447

Closed dependabot[bot] closed 6 hours ago

dependabot[bot] commented 8 hours ago

Bumps third_party/cores/ariane from 33c5d77 to e7f27c1.

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github-actions[bot] commented 6 hours ago

Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
tree_sitter_systemverilog 0 0 0 0 4490
VeribleExtractor 0 0 0 0 4494
Verible 0 0 0 0 4494
UhdmVerilator 0 0 0 0 4663
SynligYosys 0 0 0 0 4306
Verilator 0 0 0 0 4663
tree_sitter_verilog 0 0 0 0 4494
Slang 0 0 0 0 4648
yosys_slang 0 0 0 0 3845
Odin 0 0 0 0 4585
circt_verilog 0 0 0 0 4638
sv_parser 0 0 0 0 4585
Icarus 0 0 0 0 4663
moore_parse 0 0 0 0 4494
moore 0 0 0 0 4585
Sv2v_zachjs 0 0 0 0 4648
Slang_parse 0 0 0 0 4585
Yosys 1 1 0 0 4305
Surelog 0 0 0 0 4648

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